The biggest issue is simply: an HDL is not a programming language.
As such, making an HDL look like a programming language doesn't increase my expressiveness or productivity all that much. (Side note: this assumes VHDL or SystemVerilog--old-school Verilog is terribly anemic in ways that SystemVerilog mostly fixed)
Now, my testbench, on the other hand, is dramatically helped by being in a real programming language with the appropriate constructs. However, we already have cocotb (in Python!) which fits the bill there and interfaces directly with my simulators without a translation step.
The biggest issue is simply: an HDL is not a programming language.
As such, making an HDL look like a programming language doesn't increase my expressiveness or productivity all that much. (Side note: this assumes VHDL or SystemVerilog--old-school Verilog is terribly anemic in ways that SystemVerilog mostly fixed)
Now, my testbench, on the other hand, is dramatically helped by being in a real programming language with the appropriate constructs. However, we already have cocotb (in Python!) which fits the bill there and interfaces directly with my simulators without a translation step.