Run RISC-V Binaries on AMD Zen-Series CPUs via Microcode Modification

by davikron 4/9/2025, 9:54 PMwith 19 comments

by monocasaon 4/9/2025, 11:38 PM

This is not achievable.

There isn't enough rewritable microcode to do this even as a super slow hack.

And even if all of the microcode were rewritable, ucode is kind of a fallback pathway on modern x86 cores with the fast path being hardwired decode for x86 instructions.

And even if that weren't the case the microcode decode and jump is itself hardwired for x86 instruction formats.

And even if that weren't the case the microops are very non-RISC being 2 address, etc.

by rincebrainon 4/9/2025, 11:28 PM

Transmeta out here snickering that it took people this long to think of this.

by throwaway48476on 4/9/2025, 11:06 PM

The ISA front-end is not strongly coupled and the original zen had a canceled version that used aarch64.

by joguon 4/9/2025, 11:55 PM

This type of contest style recruiting just seems like a way to trick people into writing code for free, and even if you do win the prize money seems laughably small for what they're asking to receive.

by camel-cdron 4/10/2025, 6:07 AM

I think a more realistic thing would be adding a few custom OPs to make binary rewriting more performant.

Another interesting thing would be implementing a subset of RVV with AVX512 hardware primitives, although idk if/how they are exposed in micro code, amd you likely would need to use a different instruction encoding.

by snvzzon 4/10/2025, 12:34 AM

Unrealistic, yet amusing.

Fortunately, they aren't betting everything on this approach.