TH1520 with the XuanTie C910 core. Avoid. That particular platform is really incredibly slow, Cortex-A5x level. And with RVV 0.7.1 instead of 1.0 too.
I wonder what payment methods they accept.
On the site: no information.
FAQ: "You can order your Elastic Metal RV1 server directly on the order page"
click order page:
-> "create an account to view the page"
"I have a question, a problem, what can I do?
Like all Scaleway services, you can contact us officially via our support center, or informally via the Scaleway Community Slack."
click support center:
-> "create an account to view the page"
Scaleway Community Slack:
-> "your browser is not sanctioned by our strikt kompliance kommitat"
You know what, never mind.
Scaleway was also early in providing Arm servers, it's cool to see them keep bringing new stuff
It's maybe almost too early, given the performance profile of these and the current state of software compat, but the trajectory is definitely there for RISC-V. Wouldn't be surprised to see these compete strongly against ARM servers a few years from now.
eMMC for cloud seems to me like a dangerous proposition. As far as I know, they do not hold up well to write intensive workloads. I suppose you will need to use networked logging.
Interesting step, their claim of world's first RISC-V servers available in the cloud is true as far as I know.
I see they list 3 officially supported GNU/Linux distros: Debian, Ubuntu, Alpine. I wonder how mature these are on RISC-V at this point and whether they're ready for production server usage.
Doe these cpus have any cryptographic hardware acceleration? They list gpus and npus only.
I have an old atom-based kimsufi by ovh, cryptography will eat almost a full core when doing file transfer over ssh or any kind of https…
No cryptographic hardware acceleration could really be the Achilles’ tendon for this platform.
What's the recommended way to learn RISC-V assembly (including SIMD)? For ARM I just found a book I liked and did the exercises on my Mac M1 (replacing system call numbers etc and changing page sizes).
probably the things that will be most interesting to people:
- SoC T-Head 1520 CPU (C910) RV64IMAFDCV0P7_Zicsr_Zifencei_Zfh_XTheadc 4 cores 1.85 GHz (though i think the v extension on the c910 is the pre-ratification 0.7.1 v extension; see https://news.ycombinator.com/item?id=39585519 for more detail)
- 128 GB eMMC
- Debian, Ubuntu, Alpine
- between 0.96W and 1.9W per 1.8GHz core
- €15.99/month or €0.042/hour
Great option to use as a CI server / job runner if one has a project targeting RISC-V. Of course one could use emulation or put a CI runner on some board in a closet somewhere. But cloud image is convenient, so it is nice to be able to do this now, just as on x86 and ARM.
100 Mbit/s NIC? Seems a bit thin.
> We are committed to providing you with the best possible experience, but please note that the artisanal design and the youth of RISC-V processor architectures do not allow us to guarantee a specific level of service, resulting in an SLA of 0%.
This looks interesting, I have been meaning to try RISC-V outside of an emulated environment. I have a visionfive board on my desk but gave up trying to figure out how to flash a production OS. There was some shady version of Fedora they offer but I prefer to flash my own via buildroot or yocto.
These guys are unbelievable. They were the first to provide ARM servers (non-virtual, if I remember correctly), and now this. I hope they are benefitting from those innovations.
Does Docker work with RISC-V?
I couldn't find the value, but how much are they charging per month for these boxes? I see they have 4 CPU cores and 16gb of RAM.
Can we ditch virtual machines if we are packing 672 servers per rack?
I'll reiterate what I wrote before:
042€/hour per hour of compute is a great deal for developers. If you tests with cross compilation and qemu anyways and sometimes needs test/benchmark on the native hardware, then this means you can spend about 5€ and you are probably set for months if not a year.
Also, with the latest gcc you can finally target rvv 0.7.1, which is supported by these CPUs. You just write your standardized rvv 1.0 intrinsics and if you add `-march=64gcxtheadvector` gcc 14 will just generate the equivalent rvv 0.7.1: https://godbolt.org/z/va9sfEnMW