> A careful comparison between a RISC and a CISC would
> seem to us to require a complete design of the hardware and
> microcode for both, construction or simulation of the processors,
> the writing of compilers and possibly an operating system, and
> performance measurement across a variety of applications.
> Without this level of effort, claims of increased
> cost-effectiveness for a RISC are hard to support
Which of course took a while, but June 1987, Acorn Archimedes, Ā£800, 4.5 MIPS (I think that is counting VAX 11/780 as 1.0) vs MICROVAX 3500 (also 1987) 2.7 MIPS, $75k. Or VAXSTATION 2000, 0.9 MIPS, $5k.
Also in 1987, 68020 Apple Mac II and Sun 3/60 were 2-3 MIPS for $8k-$10k, less CISCy than VAX but still crazy CISCy. Much better price/performance than VAX, much worse than ARM.
> Dense code, of course, offers other advantages as well. Cache
> performance and paging performance will be better if there are
> more instructions per cache block and per page.
They are correct about that.
It is interesting that early RISC machines all had 2 instruction lengths and excellent code density: CDC6600, CRAY I, IBM 801, RISC-I. The early commercial RISCs between 1985 and 1992 (ARM, SPARC, MIPS, PA-RISC, Power(PC), Alpha) had just a single instruction length and poor code density.
Since 1995, everyone (re)introduced two instruction lengths in one way or another, culminating in the current ARMv7, RISC-V, and the stillborn nanoMIPS (1 chip produced before MIPS abandoned their own ISA in favour of RISC-V).
ARMv8 (Aarch64) is a weirdo, introduced in 2012 with a single instruction length and poor code density, ignoring the lessons of the fantastic success of ARMv7. To its credit, it is by far the most dense fixed-length 4-byte instruction ISA, easily beating A32, PowerPC, MIPS, SPARC etc. It also pretty much matches the highly variable length Amd64 which suffers a lot from pasting REX prefixes onto the i686 ISA.
But Aarch64 has poor code density compared to RISC-V (or 32 bit ARM) and I think this will ultimately be a large part of its undoing once modern Āµarch RISC-V SoCs get into mass production (including the various companies who have already announced or are working on 8-wide RISC-V cores).
> Here is an example from the VAX-11/780: in one time-sharing
> benchmark the instruction MOVC3 (a character-move instruction)
> accounts for less than 0.4% of the instruction executions, but
> for 13% of the time; it is 60th in the frequency ranking, ist in
> the time ranking.
Not mentioned by them: on the VAX-11/780, a decent memcpy() using normal instructions is faster than MOVC3.
FUD at its very best.
> A careful comparison between a RISC and a CISC would > seem to us to require a complete design of the hardware and > microcode for both, construction or simulation of the processors, > the writing of compilers and possibly an operating system, and > performance measurement across a variety of applications. > Without this level of effort, claims of increased > cost-effectiveness for a RISC are hard to support
Which of course took a while, but June 1987, Acorn Archimedes, Ā£800, 4.5 MIPS (I think that is counting VAX 11/780 as 1.0) vs MICROVAX 3500 (also 1987) 2.7 MIPS, $75k. Or VAXSTATION 2000, 0.9 MIPS, $5k.
Also in 1987, 68020 Apple Mac II and Sun 3/60 were 2-3 MIPS for $8k-$10k, less CISCy than VAX but still crazy CISCy. Much better price/performance than VAX, much worse than ARM.
> Dense code, of course, offers other advantages as well. Cache > performance and paging performance will be better if there are > more instructions per cache block and per page.
They are correct about that.
It is interesting that early RISC machines all had 2 instruction lengths and excellent code density: CDC6600, CRAY I, IBM 801, RISC-I. The early commercial RISCs between 1985 and 1992 (ARM, SPARC, MIPS, PA-RISC, Power(PC), Alpha) had just a single instruction length and poor code density.
Since 1995, everyone (re)introduced two instruction lengths in one way or another, culminating in the current ARMv7, RISC-V, and the stillborn nanoMIPS (1 chip produced before MIPS abandoned their own ISA in favour of RISC-V).
ARMv8 (Aarch64) is a weirdo, introduced in 2012 with a single instruction length and poor code density, ignoring the lessons of the fantastic success of ARMv7. To its credit, it is by far the most dense fixed-length 4-byte instruction ISA, easily beating A32, PowerPC, MIPS, SPARC etc. It also pretty much matches the highly variable length Amd64 which suffers a lot from pasting REX prefixes onto the i686 ISA.
But Aarch64 has poor code density compared to RISC-V (or 32 bit ARM) and I think this will ultimately be a large part of its undoing once modern Āµarch RISC-V SoCs get into mass production (including the various companies who have already announced or are working on 8-wide RISC-V cores).
> Here is an example from the VAX-11/780: in one time-sharing > benchmark the instruction MOVC3 (a character-move instruction) > accounts for less than 0.4% of the instruction executions, but > for 13% of the time; it is 60th in the frequency ranking, ist in > the time ranking.
Not mentioned by them: on the VAX-11/780, a decent memcpy() using normal instructions is faster than MOVC3.